Field of the Invention
The present invention relates to a composition for forming a coating type BPSG film usable in a process for producing a semiconductor device and so forth, a substrate having a film formed from the composition, and a patterning process using the composition.
Description of the Related Art
In 1980s, photo-exposure using g-beam (436 nm) or i-beam (365 nm) of mercury lamp as a light source had been widely used in the resist patterning. As a means for finer patterning, shifting to a exposure light having shorter wavelength was assumed to be effective, so that, for the mass production process of DRAM (Dynamic Random Access Memory) with 64 MB (work size of 0.25 μm or less) in 1990s and later ones, KrF excimer laser (248 nm), whose wavelength is shorter than i-beam (365 nm), had been used in place of i-beam as the exposure light source.
However, for production of DRAM with integration of 256 MB and 1 GB or higher requiring further finer processing technologies (work size of 0.2 μm or less), a light source having a further shorter wavelength was required, and thus, a photolithography using ArF excimer laser (193 nm) has been investigated seriously over a decade. It was expected at first that the ArF lithography would be applied to the fabrication of 180 nm-node devices. However, the KrF excimer lithography survived to the mass production of 130 nm-node devices, so that a full-fledged application of the ArF lithography started from the 90 nm-node.
Furthermore, mass production of the 65 nm-node devices is now underway by combining the ArF lithography with a lens having an increased numerical aperture (NA) of 0.9. For the next 45 nm-node devices, further shortening the wavelength of exposure light is progressing, and the F2 lithography with 157 nm wavelength became a candidate. However, there are many problems in the F2 lithography: cost-up of a scanner due to use of a large quantities of expensive CaF2 single crystal for a projection lens; extremely poor durability of a soft pellicle, which leads to change of an optical system due to introduction of a hard pellicle; decrease in etching resistance of a resist film, and so forth. Because of these problems, development of the F2 lithography was suspended, and ArF immersion lithography was introduced. In the ArF immersion lithography, water having a refractive index of 1.44 is introduced between a projection lens and a wafer by a partial fill method. This enables high speed scanning, and further, mass production of the 45 nm-node devices is now underway by using a lens with a NA of 1.3.
For the 32 nm-node lithography, which is a next promising fine processing technology, a lithography with an extreme-ultraviolet beam (EUV) of 13.5 nm-wavelength is considered to be a candidate. Unfortunately, this technology has problems such as needs for a higher output power of the laser, a higher sensitivity of the resist film, a higher resolution, a lower line edge roughness (LER), a non-defect MoSi laminate mask, a lower aberration of the reflective mirror, and so forth; and thus, there are innumerable problems to be solved at present. Development of the immersion lithography with a high refractive index, which is another candidate for the 32 nm-node, was suspended because of low transmittance of LUAG, a candidate for a high refractive index lens, and an inability to obtain a target value of a liquid's refractive index at 1.8. As mentioned above, in the photo-exposure used as a general technology, resolution based on the wavelength of a light source is approaching to its inherent limit.
Accordingly, development has been promoted in fine processing technology for obtaining a work size exceeding a limiting resolution of the existing ArF-immersion exposure technology. As this technology, double patterning technology is proposed. One example of the double patterning technology is a method (1) that includes forming a first photoresist pattern by first exposure and development with an interval rate of a line to a space of 1:3; processing an under layer hard mask by dry etching; laying another hard mask thereon; forming a second line pattern by subjecting the photoresist film to second exposure and development at a space obtained by the first exposure; processing the hard mask by dry etching to form the first pattern and the second pattern alternately. This method allows to form a line and space pattern with half pitch of the exposure pattern.
Also, there is another method (2) that includes forming a first photoresist pattern by first exposure and development with an interval rate of a line to a space of 3:1; processing an under layer hard mask by dry etching; forming a photoresist film thereon; forming a pattern on a remaining portion of the hard mask by second exposure; and processing the hard mask by dry etching using the pattern as a mask. In both methods, the hard mask is processed by dry etching twice, and a pattern with half pitch of the exposure pattern can be formed. The method (1) requires hard mask formation twice, while the method (2) requires hard mask formation only once, but further requires additional formation of a trench pattern which is more difficult to resolve than a line pattern.
As another example, there has been proposed a method (3) that includes forming a line pattern in X direction with a positive resist film by using a dipole light; curing the resist pattern; applying a resist composition thereon again; exposing a line pattern in Y direction by using a dipole light to form a hole pattern from the gap of the grid-like line pattern (Non-Patent Document 1). Moreover, there has also been proposed a method for halving a pitch by one-time pattern exposure by using spacer technology in which a resist pattern, an organic hard mask, or a polysilicon film having a transferred pattern is used as a core pattern, and after forming a silicon oxide film around the core pattern at a low temperature, the core pattern is removed by dry etching or other method.
Accordingly, finer processing is difficult to achieve only by using a resist film present in the upper layer, and a finer patterning process cannot be readily introduced without using a hard mask formed under the resist film. Under the circumstances, multilayer resist method is known as a method in which a hard mask is used as a resist under layer film. In this method, an intermediate film (e.g. a silicon-containing resist under layer film) whose etching selectivity is different from a photoresist film (i.e. an upper layer resist film) is formed between the upper layer resist film and a substrate to be processed, then a pattern is formed with the upper layer resist film, and the pattern is transferred to the resist under layer film by dry etching using the upper layer resist pattern as a dry etching mask, and further the pattern is transferred to the substrate to be processed or a core film of the spacer process by dry etching using the resist under layer film as a dry etching mask.
The present inventors have proposed a composition for forming a silicon-containing resist under layer film as disclosed in Patent Documents 1 and 2 for a patterning in the semiconductor manufacturing process which exceeds the limit of resolution of ArF liquid immersion lithography in recent years. However, it has inherently been used in a process exceeding the limit of resolution of the ArF liquid immersion lithography, whose difficulty is extremely high; therefore it is virtually impossible to pass through the patterning with a yield of 100%, which may result in a retry of the application of upper layer resist due to abnormalities in application of the upper layer resist or in exposure. If the above-mentioned double patterning process becomes the mainstream of the patterning process in the future, difficulty of the patterning process is further increased, and the frequency of the retrying process is expected to be higher.
The retrying process until now is to remove all the multilayered resist under layer film by dry etching, or to remove the silicon-containing resist under layer film by a removing liquid containing hydrofluoric acid, etc., after peeling the upper layer resist by a solvent, so that damage to the substrate to be processed is concerned.
On the other hand, in the cutting-edge semiconductor, technologies such as three-dimensional transistor and through interconnection, etc., have been used to improve properties of the semiconductor. In a patterning process to be used for forming such a structure in the semiconductor, patterning by the multilayer resist method has been employed. In such a patterning, after pattern formation, a step of removing the silicon-containing resist under layer film without causing damage to the pattern is occasionally required. However, main constitutional elements of the conventional silicon-containing resist under layer film and main constitutional elements of the pattern are both silicon in many cases, so that even if one wishes to selectively remove the resist under layer film, it is difficult to suppress the damage to the pattern by either of dry etching or wet etching using a hydrofluoric acid type removing liquid, because these constitutional components are similar.
In addition, there is another problem that if a silicon-containing resist under layer film is used as a mask to process an organic under layer film just under the same by dry etching, the silicon-containing resist under layer film is modified by the dry etching, and thereby hardly removed by wet etching.
Further, after forming a structure in the so-called front-end of the semiconductor, there is a process which facilitates a wiring process by flattening the structure before forming a wire on the structure. So far, a BPSG (boron phosphorus silicon glass) film is formed by the CVD method, and then the BPSG film is flattened by thermo-fusion with a heat treatment. However, in the CVD method, generation of fine grains, so-called particles cannot be avoided principally, and a special cleaning process for removing the particles is required, so that the process is inefficient.